1. Field of the Invention
The present invention relates to a semiconductor device which includes a memory cell region, a peripheral circuit region, and a boundary region in a boundary between the memory cell region and the peripheral circuit region and in which no step difference is formed in the boundary, and to a method for manufacturing the semiconductor device.
2. Description of the Related Art
A memory device, such as a DRAM (Dynamic Random Access Memory), generally comprises a memory cell region for storing information, a peripheral circuit region for controlling the writing/reading of information to this memory cell region, and a boundary region present between the memory cell region and the peripheral circuit region.
This memory cell region generally comprises a plurality of memory cells, each of which comprises a select transistor and a capacitor. In recent years, this memory device has had the problem of a decrease in the amount of charge accumulated in the capacitor as a result of the memory cells being miniaturized due to the development of microfabrication technique.
Hence, a crown-structured capacitor has been adopted in order to solve this problem. This crown-structured capacitor is constructed in such a manner that a lower electrode, a dielectric film and an upper electrode are formed within a concavely-formed opening so as to extend along the inner wall thereof, thereby increasing the area of the capacitor. Japanese Patent Laid-Open No. 7-7084 discloses a semiconductor device with this crown-structured capacitor and a method for manufacturing the semiconductor device.
When forming this crown-structured capacitor, it is important to eliminate a step difference present in a boundary between the memory cell region and the peripheral circuit region, from the viewpoint of making a process in a later interconnection step easy.
Hence, in the method disclosed in Japanese Patent Laid-Open No. 7-7084, several rows of trenches comprised of lower electrodes are formed in the boundary region between the memory cell region and the peripheral circuit region and an interlayer insulating film in the memory cell region is removed by wet etching, with at least one trench and the peripheral circuit region covered with a photoresist film.
FIGS. 20 to 31 illustrate a method for manufacturing such a related semiconductor device as shown by way of example in Japanese Patent Laid-Open No. 7-7084. First, gate oxide film 3, gate electrode 4, diffusion layer regions (source/drain regions) 5, 6, 7 and 7a, polysilicon plugs 11 and 11a, metal plugs 12, 41, 41a, 42 and 42a, bit line 8, first layer interconnects 8a and 8b, landing pad 81, lower layers 81c (two layers parallel to each other), and the like are formed on a substrate constituting the memory cell region and the peripheral circuit region. FIG. 20 is a cross-sectional view illustrating this condition, whereas FIG. 21 is a top view illustrating the upper portion of the memory cell region after the patterning of landing pad 81 and lower layers 81c.
Next, interlayer insulating film (silicon nitride film) 32 and interlayer insulating film (oxide silicon film) 24 are successively formed on the entire surface of the resulting structure. FIG. 22 is a cross-sectional view illustrating this condition. After this, cylinder hole 91 is created using a photolithographic technique and a dry etching technique, so as to penetrate through interlayer insulating films 24 and 32, thereby exposing a surface of landing pad 81 on the bottom face of cylinder hole 91. At this time, cylinder trench 91a is created in a boundary region concurrently with creating cylinder hole 91, thereby exposing lower layer 81c on the bottom of cylinder trench 91a. FIG. 23 is a cross-sectional view illustrating this condition, whereas FIG. 24 is a top view illustrating an edge of the memory cell region after the patterning of cylinder hole 91 and cylinder trench 91a.
Next, using a CVD method, first titanium nitride film 51 is grown on the entire surface of the resulting structure. Next, a photoresist film (not illustrated) is filled into cylinder hole 91 and cylinder trench 91a, and then a portion of the first titanium nitride film located upper than interlayer insulating film 24 is etched back and removed. Consequently, it is possible to obtain concave lower electrode 51 on the inner wall of cylinder hole 91 in the memory cell region and concave lower conductive region 51a on the inner wall of cylinder hole 91a in the boundary region. Next, the photoresist film is removed using an organic separating liquid. FIG. 25 is a cross-sectional view illustrating this condition, whereas FIG. 26 is a top view illustrating an edge of the memory cell region after the etching back of the titanium nitride film.
Next, using a photolithographic technique, photoresist film 96 is formed in the peripheral circuit (logic circuit) region and in part of the boundary region. At this time, alignment is performed so that at least one of two parallel lower conductive regions 51a in the boundary region is covered with the photoresist film. FIG. 27 is a cross-sectional view illustrating this condition, whereas FIG. 28 is a top view illustrating an edge of the memory cell region after the formation of photoresist film 96.
The reason for two lower conductive regions 51a being formed in this way is that, as shown in Japanese Patent Laid-Open No. 7-7084, the photoresist film is formed so that an edge thereof is shifted toward the peripheral circuit region side in some cases due to misalignment. That is, the two lower conductive regions are formed in order to prevent any portions, in which the photoresist film is not present, from being formed on the peripheral circuit (logic circuit) region, thereby preventing interlayer insulating film 24 in the peripheral circuit (logic circuit) region from being eroded by later wet etching.
Next, a portion of interlayer insulating film (oxide silicon film) 24 in the memory cell region is removed by a wet etching method using a dilute hydrofluoric acid (HF) solution. At this time, photoresist film 96 serves as a mask in the peripheral circuit region (logic circuit region) and, therefore, interlayer insulating film (oxide silicon film) 24 remains without being removed. FIG. 29 is a cross-sectional view illustrating this condition, whereas FIG. 30 is a top view illustrating an edge of the memory cell region after the removal of interlayer insulating film 24.
Next, dielectric film 52, upper electrode (second titanium nitride) 53, second layer interconnects 61 and 61a, and the like are formed, thereby finally obtaining the semiconductor device. FIG. 31 is a cross-sectional view illustrating this condition.
We have now discovered that there are the below-mentioned problems with such a semiconductor device and a method for manufacturing the semiconductor device as shown by way of example in FIGS. 21 to 30 mentioned above:    (1) The area of the boundary region becomes large due to the presence of two lower conductive regions (cylinder trenches arranged around the memory cell region). As a result, the chip area also becomes large and, therefore, the cost of manufacture increases.    (2) Since a photoresist film is used as a mask for the peripheral circuit (logic circuit) region when removing portions of the interlayer insulating film in the memory cell region and the boundary region by a wet etching method, foreign matter is produced during wet etching. That is, the photoresist film reacts with a dilute hydrofluoric acid (HF) solution at the time of wet etching and changes in quality, thus producing polymer-like foreign matter. Alternatively, watermarks or the like is produced since IPA (isopropyl alcohol) cannot be used when drying a wafer after wet etching. Consequently, the yield of manufacture degrades.    (3) A lower electrode collapses or adjacent lower electrodes come into contact with each other due to the absence of a foundation layer in the memory cell region. In particular, the lower electrode becomes easy to collapse due to surface tension produced during wet etching with a lower electrode exposed. Consequently, the yield of manufacture degrades.
Accordingly, the present inventors have recognized that it is possible to solve problems (1) to (3) mentioned above by forming a silicon nitride film which serves as a mask for the peripheral circuit (logic circuit) region and as a foundation layer in the memory cell region at the time of wet etching.